1. Field of the Invention
Embodiments of the present invention relate generally to the field of accessing a block-based storage device with a memory-mapped interface and a block-based interface.
2. Description of the Related Art
Electronic devices may require high speed access to non-volatile memory contained within these devices. Prior approaches access memory either using block access to a block storage device or memory-mapped access to a memory device. A conventional memory-mapped approach includes initiating a system call with a user program to memory-map an open file. If an underlying storage device has a memory-mapped interface, then the OS requests a physical address for address range(s) from the storage driver. The driver implements a direct access method to perform any setup operations to obtain a physical address for the given range. Then, the OS processes and updates page tables which may cause faults to read/write requests to the memory-mapped region. The OS returns a virtual address of the memory-mapped region. The user program is now able to read/write to the memory-mapped region.
If the underlying storage device is not memory-mappable, then the OS optionally caches select pages from the file into RAM and the process proceeds to the process page table operation. After the memory-mapped access setup is complete, a user program can initiate a read/write request to memory. If a requested page is mapped, then a processor resumes execution of the user program and determines if the page is located in RAM. If so, a memory controller completes the request directly to/from RAM and transfers data to the processor. If not, then the memory controller requests data from a memory-mapped capable I/O device and this device transfers data to the processor.
A memory-mapped device is generally simpler for the user application to interface with, and typically results in lower latency per request than a block-based storage device. However, the total bandwidth of a memory-mapped device will generally be lower due to reduced parallelism in comparison to a block device.
It will be appreciated that for simplicity and clarity of illustration, elements illustrated in the figures have not necessarily been drawn to scale. For example, the dimensions of some of the elements may be exaggerated relative to other elements for clarity. Further, where considered appropriate, reference numerals have been repeated among the figures to indicate corresponding or analogous elements.